Making RAM at Home

1 min read
semiconductorsdramhardwarefabricationphotolithographyclean-roomdiy-engineeringmaterials-science
View as Markdown
Originally from youtube.com
View source

My notes

Summary

A hobbyist semiconductor engineer converted a backyard shed into a class-100 clean room and built functional DRAM cells from scratch using homemade fabrication tools. The project demonstrates that the fundamental physics of DRAM - transistor gating + capacitor charge storage - can be replicated outside a commercial fab, though at microscopic scale rather than production density. The prototype holds charge for ~2 ms vs. 64+ ms for commercial DRAM, proving the concept while revealing the precision gap.

Key Insight

  • DRAM architecture is simpler than assumed: each bit = one transistor (switch) + one capacitor (charge storage). The transistor charges the cap, then disconnects; reading drains it, so every read requires an immediate rewrite (refresh cycle).
  • Three companies control global DRAM supply (Micron, Samsung, SK Hynix). New fabs take years and billions - no rapid supply response to AI-driven demand spikes.
  • Hobbyist fab stack is achievable but constrained: homemade sputter (aluminum deposition), custom microscope-stepper for photolithography, phosphorus-doped spin-on glass instead of ion implantation (too large/expensive for shed-scale). Each commercial shortcut has a DIY substitute, at cost of precision.
  • Key fabrication steps demonstrated: thermal oxidation at 1 100 °C -> photoresist patterning -> HF etching -> source/drain doping -> gate oxide growth (950 °C, 200 Å) -> aluminum liftoff metallization.
  • Punch-through effect at sub-micron gate lengths: source and drain merge at higher voltages, losing gate control. Manageable at low voltage; reveals why scaling transistors is non-trivial.
  • Measured capacitance: 12.3 fF vs. 11.x fF theoretical - within noise, showing the oxide thickness targeting was accurate.
  • Charge retention: ~2 ms (commercial target: >64 ms). Gap is due to leakage from device geometry, not a fundamental blocker - addressable with better doping profiles and oxide quality.
  • Piranha clean (H2SO4 + H2O2) is the standard last-resort surface prep before gate oxide growth; attacks organics and most metals aggressively.